Programmable integrated circuits are known in the art and include programmable logic devices ("PLDs"), Programmable Array Logic ("PALs"), and Programmable Logic Arrays ("PLAs"). Each of these programmable circuits provides an input AND logic plane followed by an OR logic plane. An output function can thus be calculated which is the sum of the products of the input terms. The logic planes are usually programmable such that the initial general layout of the planes may be customized for a particular application.
A more general approach to programmable arrays involves providing an array of distinct, uncommitted logic cells in a Programmable Gate Array ("PGA"). A programmable interconnect network is provided to interconnect the cells, and to provide data input to, and output from, the array. Customization or programming of the otherwise generally-designed logic cells and interconnect network is performed for a particular application. One such array is a Mask Programmable Gate Array ("MPGA"), wherein the configuration of the cells and the wiring network occurs when adding the final layers of metallization to an integrated circuit. A modified approach involves the use of laser-directed energy to customize the metallization pattern. Another such array is a Field Programmable Gate Array ("FPGA"), wherein the configuration can be performed by a user, in the "field." Such configuration may be effected by using electrically programmable fusible links, antifuses, memory-controlled transistors, floating-gate transistors, or the like.
A third, emerging type of programmable circuit is disclosed in the above-incorporated U.S. Patent Application entitled, "Field Programmable Memory Array." A field programmable memory array ("FPMA") may include uncommitted sub-arrays of memory cells. The sub-arrays of memory cells can be arranged in a user-defined manner using, for example, programmable address units, programmable, hierarchical data bitline structures, and programmable I/O and clocking resources. Though the functional configuration of the memory sub-arrays may vary in a user-defined manner, the physical layout of the memory sub-arrays must be determined during the layout of the integrated circuit. Because of their repetitive nature, the memory sub-arrays will likely be laid out in a regular pattern.
Discussed in the "Field Programmable Memory Array" application was a combination of an FPGA and an FPMA in a single integrated circuit to provide both programmable processing resources and programmable memory resources to a user. To effect meaningful, functional cooperation between FPGA and the FPMA circuit regions, an interface between these two regions in the integrated circuit must be defined. This interface must be designed to provide the high level of node connectivity necessary to provide data, control, and clock/reset signals to or from the sub-arrays of memory cells of the FPMA.
The interconnect network of the logic cells in the FPGA, as well as the logic cells themselves, may require connection to the resources of the FPMA. However, because of the nature of an FPGA, connectivity between all of the logic cells thereof via the interconnect network is usually an important feature and should be maintained despite the placement of an FPMA region therein. Therefore, it is desirous to maintain programmable connectivity between the logic cells of FPGA region of the integrated circuit chip, while at the same time providing connectivity to the FPMA region of the chip.
Finally, the interface should be designed to minimize the physical layout changes of an existing circuit region (e.g., an FPGA) into which a new circuit region (e.g., an FPMA) is introduced.
Therefore, what is required is an interface whereby regions of an integrated circuit having different functional characteristics can be interconnected in a manner which maintains full interconnection of circuits within the regions themselves. The interface should provide the requisite level of interconnection between the two functionally different regions, and should be implemented without significantly impacting existing physical layouts of one region into which another region is being introduced.